FPGA Implementation of Machine Learning Hardware Accelerator for Mobile Applications of Brain-Computer Interface

FPGA Implementation of Machine Learning Hardware Accelerator for Mobile Applications of Brain-Computer Interface

论文摘要

Mobile application of brain-computer interface(BCI) system is of great significance. This paper first analyzes machine learning algorithms commonly used in BCI, and extracts QR decomposition as the core step of algorithm integration to design hardware accelerators. Secondly, using Givens Rotation(GR) as implementation strategy of QR decomposition(QRD). Finally, High Level Synthesis(HLS) method is used to synthesize and implement IP cores of QRD in FPGA. QRD based IP cores are designed with floating point and fixed point for 8×8 and 62×62 matrix. Experiments show that resource consumption by fixed point implementation reduce by 40% compared to floating point implementation and speed of operations increase by more than one time. Finally, based on QRD based IP cores, matrix inversion IP cores are designed and implemented, which is at least 3 times faster than ARM Cortex-M3 platform.

论文目录

文章来源

类型: 国际会议

作者: Wen-tao SHEN,Li ZHENG,Ming LIU

来源: 2019 International Conference on Information Technology, Electrical and Electronic Engineering (ITEEE 2019) 2019-01-20

年度: 2019

分类: 基础科学,医药卫生科技,信息科技

专业: 生物学,生物医学工程,无线电电子学,自动化技术

单位: Institute of Semiconductors,Chinese Academy of Sciences,School of Electronic,Electrical and Communication Engineering,University of Chinese Academy of Sciences

分类号: R318;TN791;TP181

DOI: 10.26914/c.cnkihy.2019.078493

页码: 436-442

总页数: 7

文件大小: 718k

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FPGA Implementation of Machine Learning Hardware Accelerator for Mobile Applications of Brain-Computer Interface
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